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74ACT818 8-Bit Diagnostic Register
July 1988 Revised September 2000
74ACT818 8-Bit Diagnostic Register
General Description
The ACT818 is a high-speed, general-purpose pipeline register with an on-board diagnostic register for performing serial diagnostics and/or writable control store loading. The D-to-Y path provides an 8-bit parallel data path pipeline register for normal system operation. The diagnostic register can load parallel data to or from the pipeline register and can output data through the D input port (as in WCS loading). The 8-bit diagnostic register has multiplexer inputs that select parallel inputs from the Y-port or adjacent bits in the diagnostic register to operate as a right-shift-only register. This register can then participate in a serial loop throughout the system where normal data, address, status and control registers are replaced with ACT818 diagnostic pipeline registers. The loop can be used to scan in a complete test routine starting point (Data, Address, etc.). Then after a specified number of machine cycles it scans out the results to be inspected for the expected results. WCS loading can be accomplished using the same technique. An instruction word can be serially shifted into the shadow register and written into the WCS RAM by enabling the D output.
Features
s On-line and off-line system diagnostics s Swaps the contents of diagnostic register and output register s Diagnostic register and diagnostic testing s Cascadable for wide control words as used in microprogramming s Edge-triggered D registers s Outputs source/sink 24 mA s ACT818 has TTL-compatible inputs s ACT818 is functionally- and pin-compatible to AMD Am29818 and MMI 74S818
Applications
* Register for microprogram control store * Status register * Data register * Instruction register * Interrupt mask register * Pipeline register * General purpose register * Parallel-serial/serial-parallel converter
Ordering Code:
Order Number 74ACT818SPC Order Package N24C Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS009801
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74ACT818
Pin Descriptions
Pin Names D0-D7 SDI DCLK MODE PCLK OEY SDO Y0-Y7 Description Data Inputs Serial Data Input Diagnostics Clock Control Input Pipeline Register Clock Output Enable Input Serial Data Output Data Outputs
Functional Description
Data transfers into the diagnostic register occur on the LOW-to-HIGH transition of DCLK. Mode and SDI determine what data source will be loaded. The pipeline register is loaded on the LOW-to-HIGH transition of PCLK. Mode selects whether the data source is the data input or the diagnostic register output. Because of the independence of the clock inputs, data can be shifted in the diagnostic register via DCLK and loaded into the pipeline register from the data input via PCLK simultaneously, as long as no setup or hold times are violated. This simultaneous operation is legal.
Function Table
Inputs SDI X X L X H MODE DCLK PCLK L L H H H X Outputs SDO S7 S7 L SDI H Diagnostic Reg. SI
X X
Operation Serial Shift; D7-D0 Disabled
X
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
Diagnostic Register
Block Diagram
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74ACT818
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (I CC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC +0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 50 mA -65C to +150C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL IIN IOZ ICC ICCT VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum Quiescent Supply Current Maximum Additional ICC/Input Minimum HIGH Level Output Voltage, Y0-Y7 Outputs Minimum HIGH Level Output Voltage, D0-D7, SDO Outputs VOL Maximum LOW Level Output Voltage, Y0-Y7 Outputs Maximum LOW Level Output Voltage, D0-D7, SDO Outputs IOLD IOHD IOLD Minimum Dynamic Output Current Y0-Y7 Outputs Minimum Dynamic Output Current Y0-Y7 Outputs Minimum Dynamic Output Current D0-D7, SDO Outputs (Note 3) IOHD Minimum Dynamic Output Current D0-D7, SDO Outputs (Note 3) 4.5 5.5 4.5 5.5 5.5 5.5 5.5 5.5 0.36 0.36 0.36 0.36 0.44 0.44 0.44 0.44 75 -75 V V V V mA mA mA mA 4.5 5.5 3.86 4.86 3.76 4.76 V V IOH = -8 mA IOH = -8 mA VIN = VIL or VIH IOL = 24 mA IOL = 24 mA (Note 2) IOL = 8 mA IOL = 8 mA VOLD = 1.65V Max VOHD = 3.85V Min VOLD = 1.65V Max VOHD = 3.85V Min 4.5 5.5 3.86 4.86 3.76 4.76 V V VCC (V) 4.5 5.5 4.5 5.5 5.5 5.5 5.5 5.5 TA = +25C Typ 1.5 1.5 1.5 1.5 2.0 2.0 0.8 0.8 0.1 0.5 8.0 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 1.0 5.0 80.0 1.5 V V A A A mA VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V VIN = VCC OE = VIH VOUT = 0V, VCC VIN = VCC or GND VIN = VCC - 2.1V VCC = 5.5V VIN = VIL or VIH IOH = -24 mA IOH =-24 mA (Note 2) Units Conditions
32 -32
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Test load 50 pF, 500 to ground.
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74ACT818
AC Electrical Characteristics
VCC Symbol tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPZL tPLZ tPZL tPLZ tPZH tPHZ tPZH tPHZ Parameter Propagation Delay PCLK to Y Propagation Delay PCLK to Y Propagation Delay MODE to SDO Propagation Delay MODE to SDO Propagation Delay SDI to SDO Propagation Delay SDI to SDO Propagation Delay DCLK to SDO Propagation Delay DCLK to SDO Output Enable Time OEY to Yn Output Disable Time OEY to Yn Output Enable Time DCLK to Dn Output Disable Time DCLK to Dn Output Enable Time OEY to Yn Output Disable Time OEY to Yn Output Enable Time DCLK to Dn Output Disable Time DCLK to Dn
Note 4: Voltage Range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Min 3.0 3.0 4.0 4.0 3.5 3.5 4.5 4.5 2.5 1.5 3.0 2.0 3.0 2.5 3.0 3.0 Typ 6.0 6.5 8.0 8.0 7.5 7.5 9.0 9.5 6.0 5.5 8.0 8.5 8.0 9.0 6.5 7.5 Max 9.0 9.0 11.0 11.5 10.5 10.5 12.5 13.0 9.0 8.0 12.0 11.0 10.0 11.0 11.5 12.0
TA = -40C to +85C CL = 50 pF Min 2.5 2.5 3.5 4.0 3.0 3.5 4.0 4.0 2.5 1.0 3.0 1.5 2.5 2.0 3.0 2.0 Max 9.5 10.0 12.0 12.5 12.0 12.0 14.0 14.5 10.0 9.0 13.5 12.0 11.0 11.5 13.0 13.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
(V) (Note 4) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
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74ACT818
AC Operating Requirements
VCC Symbol tS tH tH tH tS tS tS tH tS tH tS tS tW tW Setup Time D to PCLK Hold Time D to PCLK Setup Time MODE to PCLK Hold Time MODE to PCLK Setup Time Y to DCLK Hold Time Y to DCLK Setup Time MODE to DCLK Hold Time MODE to DCLK Setup Time SDI to DCLK Hold Time SDI to DCLK Setup Time DCLK to PCLK Setup Time PCLK to DCLK Pulse Width PCLK HIGH or LOW Pulse Width DCLK HIGH or LOW
Note 5: Voltage range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Typ 1.0 0.0 2.5 -1.0 0.5 0 2.0 -0.5 2.0 -0.5 6.0 6.0 2.0 2.0 4.0 1.0 4.5 0.0 2.5 1.0 4.0 1.0 3.5 1.0 9.0 11.0 3.0 3.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 5.0 1.0 5.5 0.0 2.5 1.5 4.0 1.0 4.5 1.0 10.5 11.5 3.0 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
Parameter
(V) (Note 5) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 20 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74ACT818 8-Bit Diagnostic Register
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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